Part Number AT24C64DM
Operating Temperature -55 ~ 125°C
Storage Temperature -65 ~ 150°C
Voltage on Any Pin with Respect to Ground -1 ~ 7V
Maximum Operating Voltage 6.25V
DC Output Current 5mA

2-Wire Serial Electrically Erasable and Programmable Read-only Memory


  • Low-voltage and Standard-voltage Operation
    • – VCC = 1.7 to 5.5V
  • Internally Organized 4096 x 8, 8192 x 8
  • 2-Wire Serial Interface
  • Schmitt Trigger, Filtered Inputs for Noise Suppression
  • Bi-directional Data Transfer Protocol
  • 1MHz (5.0V) and 400KHz (1.8V Compatibility)
  • Write Protect Pin for Hardware Data Protection
  • 32-Byte Page Write Mode (Partial Page Writes Allowed)
  • Self-Timed Write Cycle (5ms max)
  • High Reliability
    • – Endurance: 1 Million Write Cycles
    • – Data Retention: 100 Years
  • Lead-free/Halogen-free Devices
  • 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead UDFN, 8-lead XDFN, 5-lead SOT23 and 8-ball VFBGA
  • Die Sales: Wafer Form, Waffle Pack and Bumped Wafers


The Atmel® AT24C32D/64D provides 32,768-/65,536-bits of serial electrically eras- able and programmable read only memory (EEPROM) organized as 4096/8192 words of 8-bits each. The device’s cascadable feature allows up to eight devices to share a common 2-wire bus. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The AT24C32D/64D is available in space saving 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead UDFN, 8-lead XDFN, 5-lead SOT23 and 8-ball VFBGA and is accessed via a 2-wire serial interface. In addition, the entire family operates from 1.7V to 5.5V.

Pin Description


The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.


The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices.


The A2, A1 and A0 pins are device address inputs that are hard wired or left not connected for hardware compatibility with other Atmel® AT24CXX devices. When the pins are hardwired, as many as eight 32K/64K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). If the pins are left floating, the A2, A1 and A0 pins will be internally pulled down to GND if the capacitive coupling to the circuit board VCC plane is <3pF. If coupling is >3pF, Atmel recommends connecting the address pins to GND.


The write protect input, when connected to GND, allows normal write operations. When WP is connected high to VCC, all write operations to the memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down to GND if the capacitive coupling to the circuit board VCC plane is <3pF. If coupling is >3pF, Atmel recommends connecting the pin to GND.

Memory Organization

Atmel AT24C32D/64D, 32/64K SERIAL EEPROM

The 32K/64K is internally organized as 128/256 pages of 32-bytes each. Random word addressing requires a 12-/13-bit data word address.

Device Operation


The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to “Data Validity” diagram). Data changes during SCL high periods will indicate a start or stop condition as defined below.


A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to “Start and Stop Definition” diagram).


A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to “Start and Stop Definition” diagram).


All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word.


The Atmel® AT24C32D/64D features a low power standby mode which is enabled:

  • Upon power-up
  • After the receipt of the Stop bit and the completion of any internal operations.


After an interruption in protocol, power loss or system reset, and 2-wire part can be protocol reset by following these steps:

  • Create a start bit condition
  • Clock nine cycles
  • Create another start bit followed by stop bit condition as shown below.

The device is ready for next communication after above steps have been completed.

Device Addressing

The 32K/64K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure 7-1 on page 10 ). The device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all 2-wire EEPROM devices.

The 32K/64K uses the three device address bits A2, A1, A0 to allow as many as eight devices on the same bus. These bits must compare to their corresponding hardwired input pins.

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