NM93C06M8

Manufacturer FAIRCHILD SEMICONDUCTOR
Part Number NM93C06M8
Operating Current MAX 1mA
Standby Current MAX 50μA

NM93C06 256-Bit Serial CMOS EEPROM (MICROWIRE™ Synchronous Bus) FAIRCHILD SEMICONDUCTOR

General Description

NM93C06 is a 256-bit CMOS non-volatile EEPROM organized as 16 x 16-bit array. This device features MICROWIRE interface which is a 4-wire serial bus with chipselect (CS), clock (SK), data input (DI) and data output (DO) signals. This interface is compatible to many of standard Microcontrollers and Microprocessors. There are 7 instructions implemented on the NM93C06 for various Read, Write, Erase, and Write Enable/Disable operations. This device is fabricated using Fairchild Semiconductor floating-gate CMOS process for high reliability, high endurance and low power consumption.

“LZ” and “L” versions of NM93C06 offer very low standby current making them suitable for low power applications. This device is offered in both SO and TSSOP packages for small space considerations.

Features

  • Wide VCC 2.7V - 5.5V
  • Typical active current of 200µA
    • 10µA standby current typical
    • 1µA standby current typical (L)
    • 0.1µA standby current typical (LZ)
  • No Erase instruction required before Write instruction
  • Self timed write cycle
  • Device status during programming cycles
  • 40 year data retention
  • Endurance: 1,000,000 data changes
  • Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP

Pin Description

Chip Select (CS)

This is an active high input pin to NM93C06 EEPROM (the device) and is generated by a master that is controlling the device. A high level on this pin selects the device and a low level deselects the device. All serial communications with the device is enabled only when this pin is held high. However this pin cannot be permanently tied high, as a rising edge on this signal is required to reset the internal state-machine to accept a new cycle and a falling edge to initiate an internal programming after a write cycle. All activity on the SK, DI and DO pins are ignored while CS is held low.

Serial Clock (SK)

This is an input pin to the device and is generated by the master that is controlling the device. This is a clock signal that synchronizes the communication between a master and the device. All input information (DI) to the device is latched on the rising edge of this clock input, while output data (DO) from the device is driven from the rising edge of this clock input. This pin is gated by CS signal.

Serial Input (DI)

This is an input pin to the device and is generated by the master that is controlling the device. The master transfers Input information (Start bit, Opcode bits, Array addresses and Data) serially via this pin into the device. This Input information is latched on the rising edge of the SCK. This pin is gated by CS signal.

Serial Output (DO)

This is an output pin from the device and is used to transfer Output data via this pin to the controlling master. Output data is serially shifted out on this pin from the rising edge of the SCK. This pin is active only when the device is selected.

Microwire Interface

A typical communication on the Microwire bus is made through the CS, SK, DI and DO signals. To facilitate various operations on the Memory array, a set of 7 instructions are implemented on NM93C06. The format of each instruction is listed under Table 1.

Instruction

Each of the 7 instructions is explained under individual instruction descriptions.

Start bit

This is a 1-bit field and is the first bit that is clocked into the device when a Microwire cycle starts. This bit has to be “1” for a valid cycle to begin. Any number of preceding “0” can be clocked into the device before clocking a “1”.

Opcode

This is a 2-bit field and should immediately follow the start bit. These two bits (along with 2 MSB of address field) select a particular instruction to be executed.

Address Field

This is a 6-bit field and should immediately follow the Opcode bits. In NM93C06, only the LSB bits are used for address decoding during READ, WRITE and ERASE instructions. During these three instructions (READ, WRITE and ERASE) the MSB 2 bits are "don't care" (can be 0 or 1).During all other instructions, the MSB 2 bits are used to decode instruction (along with Opcode bits).

Data Field

This is a 16-bit field and should immediately follow the Address bits. Only the WRITE and WRALL instructions require this field. D15 (MSB) is clocked first and D0 (LSB) is clocked last (both during writes as well as reads).

Functional Description

A typical Microwire cycle starts by first selecting the device (bringing the CS signal high). Once the device is selected, a valid Start bit (“1”) should be issued to properly recognize the cycle. Following this, the 2-bit opcode of appropriate instruction should be issued. After the opcode bits, the 6-bit address information should be issued. For certain instructions, some of these 6 bits are don’t care values (can be “0” or “1”), but they should still be issued. Following the address information

Other Parts