PC28F128J3D-75

Manufacturer NUMONYX B.V
Part Number PC28F128J3D-75
Package Height 1.2mm
Standoff 0.05mm
Package Body Thickness 0.965 ~ 1.025mm
Lead Width 0.1 ~ 0.2mm
Lead Thickness 0.1 ~ 0.2mm
Package Body Length 18.2 ~ 18.6mm
Package Body Width 13.8 ~ 14.2mm

Datasheet

Product Features

  • Architecture
    • — High-density symmetrical 128 Kbyte blocks
    • — 256 Mbit (256 blocks)
    • — 128 Mbit (128 blocks)
    • — 64 Mbit (64 blocks)
    • — 32 Mbit (32 blocks)
  • Performance
  • +— 75 ns Initial Access Speed (128/64/32 Mbit densities)
    • — 95 ns Initial Access Speed (256 Mbit only)
    • — 25 ns 8-word and 4-word Asynchronous page-mode reads
    • — 32-Byte Write buffer
    • — 4 µs per Byte Effective programming time
  • System Voltage and Power
    • — VCC = 2.7 V to 3.6 V
    • — VCCQ = 2.7 V to 3.6 V
  • Packaging
    • — 56-Lead TSOP package (32, 64, 128 Mbit only)
    • — 64-Ball Numonyx Easy BGA package (32, 42, 128 and 256 Mbit)
  • Security
    • — Enhanced security options for codeprotection
  • +— 128-bit Protection Register
    • — 64-bit Unique device identifier
    • — 64-bit User-programmable OTP cells
    • — Absolute protection with VPEN = GND
    • — Individual block locking
    • — Block erase/program lockout during power transitions
  • Software
    • — Program and erase suspend support
    • — Flash Data Integrator (FDI), Common Flash Interface (CFI) Compatible
  • Quality and Reliability
    • — Operating temperature: -40 °C to +85 °C
    • — 100K Minimum erase cycles per block
    • — 0.13 µm ETOX™ VIII Process

Functional Overview

The Numonyx™ Embedded Flash Memory (J3 v. D) family contains high-density memory organized in any of the following configurations:

  • 32 Mbytes or 16 Mword (256-Mbit), organized as two-hundred-fifty-six 128-Kbyte (131,072 bytes) erase blocks- Users should be aware that this density is not offered in a monolithic part and the device is made up of 2x128-Mb devices.
  • 16 Mbytes or 8 Mword (128-Mbit), organized as one-hundred-twenty-eight 128 Kbyte erase blocks
  • 8 Mbytes or 4 Mword (64-Mbit), organized as sixty-four 128-Kbyte erase blocks
  • 4 Mbytes or 2 Mword (32-Mbit), organized as thirty-two 128-Kbyte erase blocks

These devices can be accessed as 8- or 16-bit words. See Figure 1, “Memory Block Diagram (32, 64 and 128 Mbit)” on page 10 for further details.

A 128-bit Protection Register has multiple uses, including unique flash device identification.

The Numonyx™ Embedded Flash Memory (J3 v. D) device includes new security features that were not available on the (previous) 0.25µm and 0.18µm versions of the J3 family. These new security features prevent altering of code through different protection schemes that can be implemented, based on user requirements.

The Numonyx™ Embedded Flash Memory (J3 v. D) device optimized architecture and interface dramatically increases read performance by supporting page-mode reads. This read mode is ideal for non-clock memory systems.

A Common Flash Interface (CFI) permits software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward- and backward-compatible software support for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility.

Scalable Command Set (SCS) allows a single, simple software driver in all host systems to work with all SCS-compliant flash memory devices, independent of system-level packaging (e.g., memory card, SIMM, or direct-to-board placement). Additionally, SCS provides the highest system/device data transfer rates and minimizes device and system-level implementation costs.

A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, program, and lock-bit configuration operations.

A block erase operation erases one of the device’s 128-Kbyte blocks typically within one second, independent of other blocks. Each block can be independently erased 100,000 times. Block erase suspend mode allows system software to suspend block erase to read or program data from any other block. Similarly, program suspend allows system software to suspend programming (byte/word program and write-to-buffer operations) to read data or execute code from any other block that is not being suspended.

Each device incorporates a Write Buffer of 32 bytes (16 words) to allow optimum programming performance. By using the Write Buffer, data is programmed in buffer increments.

Blocks are selectively and individually lockable in-system. Individual block locking uses block lock-bits to lock and unlock blocks. Block lock-bits gate block erase and program operations. Lock-bit configuration operations set and clear lock-bits (using the Set Block Lock-Bit and Clear Block Lock-Bits commands).

The Status Register indicates when the WSM’s block erase, program, or lock-bit configuration operation is finished.

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