|Manufacturer part number||MAX6953EAX+|
|Operating Supply Voltage||2.7 ~ 5.5V|
|Operating Supply Current||12 ~ 15mA|
|Master Clock Frequency||4MHz|
|Dead Clock Protection||90kHz|
|OSC Internal/External Detection Threshold||1.7V|
|OSC High Time||50ns|
|OSC Low Time||50ns|
|Slow Segment Blink Period||1s|
|Fast Segment Blink Period||0.5s|
|Fast or Slow Segment Blink||49.5 ~ 50.5%|
|Column Drive Source Current||-32 ~ -48mA|
The MAX6953 is a compact cathode-row display driver that interfaces microprocessors to 5 ✕ 7 dot-matrix LED displays through an I2C™-compatible serial interface. The MAX6953 drives up to four digits (140 LEDs). Included on-chip are an ASCII 104-character font, multiplex scan circuitry, column and row drivers, and static RAM that stores each digit, as well as font data for 24 user-definable characters. The segment current for the LEDs is set by an internal digit-by-digit digital brightness control.
The device includes a low-power shutdown mode, segment blinking (synchronized across multiple drivers, if desired), and a test mode that forces all LEDs on. The LED drivers are slew-rate limited to reduce EMI.
For an SPI™-compatible version, refer to the MAX6952 data sheet. An EV kit is available for the MAX6952.
The MAX6953 is a serially interfaced display driver that can drive four digits of 5 ✕ 7 cathode-row dot-matrix displays. The MAX6953 can drive either four monocolor digits (Table 1) or two bicolor digits (Table 2). The MAX6953 includes a 128-character font map comprising 104 predefined characters and 24 user-definable characters. The predefined characters follow the Arial font, with the addition of the following common symbols: £, <, ¥, °, µ, ±, ↑, and ↓. The 24 user-definable characters are uploaded by the user into on-chip RAM through the serial interface and are lost when the device is powered down. Figure 1 is the MAX6953 functional diagram.
The MAX6953 operates as a slave that sends and receives data through an I2C-compatible 2-wire interface. The interface uses a serial data line (SDA) and a serial clock line (SCL) to achieve bidirectional communication between master(s) and slave(s). A master (typically a microcontroller) initiates all data transfers to and from the MAX6953, and generates the SCL clock that synchronizes the data transfer (Figure 2).
The MAX6953 SDA line operates as both an input and an open-drain output. A pullup resistor, typically 4.7kΩ, is required on the SDA. The MAX6953 SCL line operates only as an input. A pullup resistor, typically 4.7kΩ, is required on SCL if there are multiple masters on the 2-wire interface, or if the master in a single-master system has an open-drain SCL output.
Each transmission consists of a START condition (Figure 3) sent by a master, followed by the MAX6953 7-bit slave address plus R/W bit (Figure 6), a register address byte, 1 or more data bytes, and finally a STOP condition (Figure 3).
Both SCL and SDA remain high when the interface is not busy. A master signals the beginning of a transmission with a START (S) condition by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP (P) condition by transitioning the SDA from low to high while SCL is high. The bus is then free for another transmission (Figure 3).
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable while SCL is high (Figure 4).
The acknowledge bit is a clocked 9th bit that the recipient uses to handshake receipt of each byte of data (Figure 5). Thus, each byte transferred effectively requires 9 bits. The master generates the 9th clock pulse, and the recipient pulls down SDA during the acknowledge clock pulse, such that the SDA line is stable low during the high period of the clock pulse. When the master is transmitting to the MAX6953, the MAX6953 generates the acknowledge bit because the MAX6953 is the recipient. When the MAX6953 is transmitting to the master, the master generates the acknowledge bit because the master is the recipient.
The MAX6953 has a 7-bit-long slave address (Figure 6). The eighth bit following the 7-bit slave address is the R/W bit. It is low for a write command, high for a read command.
The first 3 bits (MSBs) of the MAX6953 slave address are always 101. Slave address bits A3, A2, A1, and A0 are selected by the address input pins AD1 and AD0. These two input pins may be connected to GND, V+, SDA, or SCL. The MAX6953 has 16 possible slave addresses (Table 3) and therefore a maximum of 16 MAX6953 devices may share the same interface.